Tokyo Electron
The Tokyo Electron Clean Track ACT8 is an industry-standard wafer coater and developer for photolithography. The Clean Track ACT8 supports DUV lithography with an in-line exposure unit interface, ULPA chemical filters, and high-precision ovens. The Clean Track ACT8 is configured for 100 mm wafers with optional conversion to 150 mm, and is also available for 8 inch wafers.[1][2][3]

Wafer size
Interface Unit (IRA) for Canon FPA-3000 i5 stepper including one multi-buffer unit and Wafer edge exposure (WEE)
Produced
1997–
Gas delivery
Chemical Cabinet 2:[3]
The Tokyo Electron Clean Track Act 8 is a wafer coater and developer track for photolithography-related wet processing.
The Clean Track Act 8 is a mature semiconductor track system used with resist coating, development, and related bake and chill steps in a clean environment.
The Act 8 is used as part of a lithography cluster rather than as a standalone wet bench.[1]
The Clean Track Act 8 is used for photoresist coating and development in semiconductor lithography.[2][3][1]
The Act 8 supports adhesion promotion, bottom-layer coating, edge-bead management, and thermal conditioning within a resist process flow.[1]
| Designation | Generation | Vintage | Changes | Source |
|---|---|---|---|---|
| Clean Track Act 8 | — | 2001 | One source lists 2001 Vintage and another lists 2002 Vintage for the same model. | Equipment inventory listing[3] |
| Dual block | — | 1999 | Dual block configuration, 2C/2D, 6 inch wafers | Equipment inventory listing[4] |
| Single block | — | 2002 | Single block, 8 inch wafers, with interface for Canon stepper | Equipment inventory listing[2] |
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It is a wet processing and clean track system used for wafer handling and surface preparation in semiconductor manufacturing.
It moves wafers through controlled wet process modules that clean, rinse, dry, or otherwise condition the wafer surface before later fabrication steps.
Because these systems handle wafers in preparation steps where particles, residues, or surface variation can affect downstream patterning and device formation.
It is typically used in the front-end portion of wafer processing, where surface condition must be controlled before later lithography or other process operations.
The following facts about the Clean Track Act 8 are absent from this record as of this revision. First-hand knowledge or a citation closes a gap; every submission is reviewed before publication.
The control-system platform and OS era of the Clean Track Act 8 are not on record.
Answerable by: an engineer who operated it or OEM installation records
No publicly documented failure modes or field errata for the Clean Track Act 8 are on record.
Answerable by: a field service engineer, process engineer, or maintenance technician
The process node or technology generation of the Clean Track Act 8 is not on record.
Answerable by: an OEM datasheet or a fab qualification report
No publicly documented compatible parts, consumables, or accessories for the Clean Track Act 8 are on record.
Answerable by: an OEM parts catalog or a service engineer
No publicly hosted manuals, SOPs, or datasheets for the Clean Track Act 8 are on record.
Answerable by: university cleanroom staff or an OEM application specialist
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Last updated Oct 7, 2026.
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