Comparison ledger
SPTS APS, Tegal 1512e, side by side. Every value shown is drawn from the cited encyclopedia entries.
| Attribute | APSSPTS | 1512eTegal |
|---|---|---|
| OEM | SPTS | Tegal |
| Category | Etch | Etch |
| Wafer size | — | — |
| Process node | — | — |
| Introduced | — | — |
| Production run | — | — |
| Lifecycle | — | — |
| Lifecycle milestones | — | — |
| Control system | — | — |
| Generation | — | — |
| Family | SPTS APS | Tegal 1512e |
| Specifications | ||
| System type | ICP-based high density plasma source[1] | — |
| Optimization target | Dielectric etching[1] | — |
| Processing mode | Single wafer processing[1] | — |
| Clamping | Electrostatic clamping[1] | — |
| End-point detection | Optical Emission Spectroscopy (EOS) and laser reflectometry/interferometry[1] | — |
| Gases available | O2, Ar, CHF3, He, C4F8, SF6, H2[1] | — |
| Plasma source type | ICP (inductively coupled plasma) high density plasma source[1] | — |
| Available gases | O2 (0-100 sccm), Ar (0-100 sccm), CHF3 (0-100 sccm), He (0-500 sccm), C4F8 (0-100 sccm), SF6 (0-100 sccm & 0-500 sccm), H2 (0-50 sccm)[1] | — |
| Wafer clamping | Electrostatic clamping (no EBR required)[1] | — |
| Wafer voltage biasing | Independent from the ICP[1] | — |
| Process chamber | Single wafer processing with loadlock[1] | — |
| Process type | ICP-based high density plasma source[1] | — |
| Etch materials | Dielectrics: SiO2, SixNy, SiC, Al2O3, glass types[1] | — |
| Wafer bias | Wafer voltage biasing independent from the ICP[1] | — |
| Wafer handling | Loadlock/chamber transfers for single wafer processing[1] | — |
| Automation | Control software offering fully automated processes[1] | — |
| Process gases | O2 (0-100 sccm), He (0-500 sccm), SF6 (0-100 sccm), H2 (0-50 sccm), plus Ar, CHF3, C4F8[1] | — |
| Stated processes | BARC_Slow, Si3N4_Smooth, SiO2_PR_1:1, SiO2_PR_2:1, SiO2_PR_3:1, SiO2_PR_3:1_SOFT, SiO2_PR_5:1, SiO2_PR_soft, Pi_vertical, Pi_tapered, Fused_silica, Pyrex, LiNbO3_wafers, Chamber clean[1] | — |
| Chuck temperature | 10 °C for most processes, 20 °C for fused silica, 25 °C for Pyrex, -10 °C for LiNbO3[1] | — |
| Maximum etch time | 20 minutes for processes marked with *; longer etches are split into steps with an automatic O2 dry clean between each[1] | — |
| Wafer cooling check | Helium leak-up rate (LUR) must not exceed 200 mtorr/min[1] | — |
| Plasma source | ICP-based high density plasma source[1] | — |
| Wafer biasing | Independent from ICP[1] | — |
| Tool type | — | Industrial RIE plasma etcher system[2] |
| Stated configuration | — | With modules assembly for CI-4222[2] |
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